Logical Effort

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Introduction

In today’s digital world the most important aspect of any processor is how fast can it function and support multiple applications. Often, the chip  design engineers are confronted with bewildering questions in the design process of a logic:

  • What is the best topology to represent a given function ?
  • How many logic stages provides the least delay ?
  • How wide the transistors should be in order to have the design optimized for area?

Logic designer often use Logical Effort to arrive at these conclusions. It uses a simple model for delay calculations and helps to make rapid comparisons between alternative structures.

CMOS inverter and sizing ratio:

As we all know, gates are made up of transistors. The most basic gate is the NOT gate ,famously known as an inverter. Once the properties and operations of the basic inverter are clearly understood, designing more complex structures such as NAND gates, adders, multipliers and even a full scale microprocessor is greatly simplified.

CMOS inverter

Figure 1: CMOS Inverter

Figure 1, shows the circuit diagram of a CMOS inverter. Here, the input to the  inverter is designated as \(A\) and output is designated as \(A^{*}\). Important thing to note here is that the small signal model of the inverter with sizing \(2:1\) is \(3*C_{in}\).Now, the question is, why is the sizing taken to be \(2:1\) ?. The major concept behind it revolves around the switching time or \(t_p\)

When the input is \(1\) (logic High), transistor N-MOS is conducting and P-mos is not conducting and hence the charge stored in output capacitor discharges, hence the output = \(0\) (logic Low). Consequently when the input is \(0\) (logic Low), N-MOS is not in conduction mode while P-MOS is in conduction mode hence the output capacitor charges, i.e, output = 1 (logic High). Since this charging and discharging takes some time (\( \propto R_{eqn} \times C_{L} \)),  there will always be some delay or transition between the change in input and output. This is the major source of delay. Since both transistors don’t have similar properties, the individual gate charging-discharging will be different. Hence, the gate sizing should be done in such a way that the resultant delay should be minimum.

Figure 2 depicts the gate dimensions (\(W\) and \(L\)) on a N-type MOSFET. The ratio of \(W / L\) ratio of PMOS to that of the NMOS transistor is called transistor sizing ration \(\beta\). Normally, the PMOS and NMOS components have the same channel length \(L=L_{p}=L_{n}\)  as dictated by the minimum feature size of a given process technology.  In a static CMOS design, the driving strengths of the NMOS and the PMOS transistors are balanced by making the PMOS section wider than the NMOS section. Generally, the width of the PMOS section is chosen as 2 to 4 times the width of the NMOS section. This is done to maximize noise margins and to obtain symmetrical properties between the PMOS and NMOS transistor.

N-MOSFET with dimensions marked

Figure 2: N-MOSFET with dimensions marked

Figure 3, shows the definition of various timing parameters used to characterize logic gates.  With respect to the output of a logic gate, the following timing parameters are relevant for this discussion.

Definition of timing parameters of logic gates

Figure 3: Definition of timing parameters of logic gates

  • \(t_{pHL}\)  = The amount of time taken to change the output from “high to low” level when the input changes. It is measured between 90% and 10% level of the amplitude of the output signal.
  • \(t_{pLH}\)=  The amount of time taken to change the output from “low to high” level when the input changes. It is measured between 10% and 90% level of the amplitude of the output signal
  • \(t_p\)= The average time taken to change the output , computed as \(t_p= (t_{pHL}+t_{pLH})/2\)

Figure 4, shows the propagation delay of CMOS inverter as a function of sizing ratio \(\beta\). As we can see from the graph \(t_{pLH} = t_{pHL}\) when \(\beta\) is slightly greater than \(2\). But \(t_p\) is least when \(\beta\) is slightly lesser than \(2\). Hence, in general the transistor sizing ratio is taken as \(\beta=2\).

gate sizing and timing parameters of CMOS
Figure 4: Propagation delay of CMOS inverter as a function of sizing ratio β

Inverter delay

Let’s assume a symmetrical inverter with identical rise-time and fall-time properties. Let \(C_L\) be the \(loading \; capacitance\) which is composed on intrinsic capacitance \(C_{int}\) and the capacitance due to extrinsic components \(C_{ext}\).

$$ C_L = C_{int} + C_{ext} $$

Given the \(equivalent \; resistance\) of the gate \(R_{eq}\) and load capacitance \(C_L\), the propagation delay is given by

$$\begin{align*} t_p & = 0.69 \times R_{eq} \times C_L \\ & = 0.69 \times R_{eq} \left( C_{int}+C_{ext} \right ) \\ & = 0.69 \times R_{eq} \times C_{int} \left( 1+ \frac{C_{ext}}{C_{int}} \right) \\ & = t_{p0} \left (1+ \frac{C_{ext}}{C_{int}} \right ) \end{align*}$$

where \(t_{p0} = 0.69 \times R_{eq} \times C_{int} \) is the delay of inverter loaded by its intrinsic capacitance and is called \(intrinsic \; or \; unloaded \; delay\).

Logical Effort Delay Model

As we know, the delay (\(d\)) of logic gates have two components:
$$ d=p + f $$
where, \(p\) – Parasitic delay – is the intrinsic delay of the gate
\(f\) – Effort delay

\(Effort \; delay\) has two components, logical effort (\(g\)) and electrical effort (\(h=C_{out}/C_{in}\)). The effort delay is given by \(f=g \times h\).

\(Electrical \; effort\) can be defined as the effective fanout of the gate, or the ratio of input capacitance \(C_{in}\) of gate to that of load.

\(Logical \; effort\) is defined as the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. It is defined as the number of times worse it is at delivering output current than would be an inverter with identical input capacitance.

Logical effort (\(g\)) depends upon following parameters:

  • Complexity of the logic function
  • Depends mainly  on topology, not sizing.
  • To a very little extent it may depend on the electrical process of the fabrication.

The logical effort heavily depends upon the topology because every topology has different resultant input capacitance which influences the overall logical effort

A NAND gate is shown in Figure 5. Here input capacitance for input A or B is \(4 \times C_{in}\) while the input capacitance for Inverter was \( 3 \times C_{in}\). The logical effort of Inverter is considered to be \(1\), or consider it to be a reference for all the delay oriented calculations in transistor logic. Hence the logical effort of NAND gate will be \(4/3\).

NAND gate

Figure 5: NAND gate

Following table shows the logical efforts of other common gates/topologies

Logical efforts of common gates

Table 1: Logical efforts of common gates

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